The use of mobile, handheld or fixed wireless devices for voice and data communications, monitoring, tracking, controlling, test and measurement has been growing prolifically in recent years as further advances in miniaturized, lower power, low cost electronics are achieved. Wireless terminals and networks are now used for numerous industrial applications including environmental monitoring, smart metering, asset tracking, and financial transactions. Whether for personal or industrial use, users are looking for increased functionality and further miniaturization of wireless devices.
Wireless sensor systems and sensor networks are finding applications in many fields. Miniaturized sensors are now available for monitoring a wide variety of biomedical, physical, chemical and environmental parameters. Elimination of wired connections is particularly desirable for sensor systems for bio-medical monitoring and space applications.
Integration of analog, digital and RF electronics for such applications presents a number of challenges. In particular, miniaturized RF electronics require innovative designs to achieve compact yet efficient wireless systems. Typically, a large part of most wireless devices is devoted to a power supply, the antenna, and wireless transmitter (TX) and receiver (RX) circuitry. For example, in a typical smart mobile phone, only 10% of components are electronics, while 90% is passives, boards and interconnect, with the battery and antenna taking up a large part of the volume. Consequently, a significant amount of research is currently being directed to developing components with reduced size and lower power operation, and particularly miniaturized antennas.
Much recent research is focused on System-on-Chip (SoC) and System-on-Package (SoP) solutions. Performance improvements in advanced CMOS integrated circuit (IC) technology have paved the way for integration of RF components with analog and digital circuits on a single chip. RF CMOS devices that exhibit high cut-off frequencies, high performance integrated passives, and lower operating voltages, potentially allow for development of SoC solutions using lower cost standard process technologies. SoC systems have already been widely accepted for applications such as wireless LAN, Bluetooth, and are making inroads into cellular transceivers, GPS receivers, and wireless sensor networks. On the other hand, substrate noise and low Q passives remain a challenge for efficient CMOS SoC implementations (see for example: A. Natarajan, A. Komijani, X. Guan, A. Babakhani, A. Hajimiri, “A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 12, pp. 2807-2819, December 2006. and M. B. Nejad, H. Tenhunen, L. Zheng, “Chip-Package and Antenna Co-Design of a Tunable UWB Transmitter in System-on-Package with On-Chip versus Off-Chip Passives,” Electronics System integration Technology Conference, 2006. 1st, vol. 1, pp. 291-298, September 2006).
SoP solutions provide for use thin film components and embedded passives instead of discrete components. To provide appropriate substrates for an antenna, there is interest in use of low loss substrates such as ceramics, and in particular, Low Temperature Co-fired Ceramic (LTCC) packaging substrates. These may be used in multi-layered packaging, and allow for embedding of passive components, and vertical integration of RF modules. While SoC is a more size efficient approach, on-chip antennas are usually very inefficient when implemented in silicon technology because of the lossy nature of low resistivity silicon substrates.
In known implementations of RF circuits using LTCC packaging, generally, the RF circuits are connected to the feed line of an LTCC package antenna through bond wires or solder balls (see for example: J. Lee, N. Kidera, S. Pinel, J. Laskar, M. Tentzeris, “Fully Integrated Passive Front-End Solutions for a V-band LTCC Wireless System,” Antennas and Wireless Propagation Letters, IEEE, pp. 285-288, 2007; R. Li, et.al., “Design of compact stacked-patch antennas in LTCC multilayer packaging modules for wireless applications,” Advanced Packaging, IEEE Transactions on, vol. 27, pp. 581-589, November 2004; I. Wolff, “Design and Technology of Microwave and Millimeter wave LTCC Circuits and Systems,” Signals, Systems and Electronics, International Symposium on, pp. 505-512, August 2007). Typically, this arrangement requires an isolating buffer amplifier and bond pads on the chip. Moreover, these antennas must be matched to the RF circuits through matching elements. This approach not only requires a number of design steps, and increases cost and overall power consumption, but the presence of bond wires also makes the module less attractive.
Aperture coupling is a well-established technique for non-contact or wireless feeding of microstrip patch antennas. For example, a silicon based aperture coupled patch antenna has been demonstrated using a conventional microstrip feed line (K. Chan, E. Lee, P. Gardner, T. Dodgson, “Differential aperture coupling technique for passive and active integrated antenna design,” Microwaves, Antennas & Propagation, IET, pp. 458-464, April 2007). However, this only eliminates the physical connection between the feed line and the antenna; the connections and components required between the integrated circuit (IC) and the antenna feed line cannot be removed. In theory, a parasitic coupling approach could be used to couple an array of patches to the IC (T. Seki, K. Nishikawa, K. Cho, “Multi-Layer Parasitic Microstrip Array Antenna on LTCC Substrate for Millimeter-Wave System-on-Package,” European Microwave Conference, pp. 1393-1396, October 2003). However, the latter approach has not been demonstrated in chip-to-package coupling.
Miniaturization of the antenna dimensions is affected by operating frequency. Antenna dimensions are a significant fraction of a wavelength in dimension, and therefore, for systems running at lower frequencies, such as the Unlicensed National Information Infrastructure (U-NIII) 5.2 GHz band, which is the international standard for indoor medical applications, antenna designs are quite large compared with those for higher frequency operation.
Another consideration is data rate. Design requirements for short range, lower frequency, wireless communications, e.g. transmission of low data rate sensor data, for example, are typically constrained by size and power consumption, rather than by requirements for high data rate or long transmission range for communications applications.
Also, regardless of frequency band, lossy substrates, parasitic coupling and interference from on-chip circuitry, or, e.g. conductive layers such as interconnect, or metal components such as batteries, in the vicinity of an antenna, can affect the design and performance. Modeling and simulations that take into account these effects, and characterization of on-chip antennas by measurement of actual antenna gain and radiation pattern is complex.
In the higher frequency ranges, transceivers with on-chip antennas have been demonstrated at 77 GHz using non-standard process technology with additional process steps (I. Wolff, “Design and Technology of Microwave and Millimeter wave LTCC Circuits and Systems,” Signals, Systems and Electronics, International Symposium on, pp. 505-512, August 2007), and at 24 GHz, on a high resistivity SiGe platform (D. M. Pozar, “A microstrip antenna aperture coupled to a microstrip line,” IEEE Electron Letters, vol. 21, no. 2, pp. 49-50, January 17, 1985).
A 5.2 GHz PLL VCO TX with an on-chip antenna that radiates with reasonable efficiency is disclosed in Canadian Patent application no. CA 2,547,372, and in a related publication (P. H. R. Popplewell, V. Karam, A. Shamim, J. Rogers, M. Cloutier and C. Plett, “5.2 GHz self-powered lock and roll radio using VCO injection-locking and on-chip antennas,” Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp. 4 pp.-5206, 2006). Factors that need to be considered in the design of the on-chip antenna for the latter PLL VCO TX are discussed in related publications. There is a tradeoff in design to optimize both the radiation and inductive characteristics of the antenna (A. Shamim, P. Popplewell, V. Karam, L. Roy, J. Rogers and C. Plett, “5.2 GHz On-Chip Antenna/Inductor for Short Range Wireless Communication Applications,” Antenna Technology Small Antennas and Novel Metamaterials, 2006 IEEE International Workshop on, pp. 213-216, 2006; and A. Shamim, P. Popplewell, V. Karam, L. Roy, J. Rogers and C. Plett, “Silicon Differential Antenna/Inductor for Short Range Wireless Communication Applications,” Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on, pp. 94-97, 2006). Antenna performance may be adversely affected by parasitic coupling and by interference between the antenna and the circuitry surrounding the on-chip antenna.
Thus, although circuits with on-chip antennas have been demonstrated, actual performance of most of these antennas has not been characterized, and in practice, on-chip antennas are not usually implemented because of the above-mentioned problems with lossy substrates, interference issues and characterization challenges.
Therefore, there is a need for further advances in miniaturization of low power and low cost wireless transmitter and receiver systems, particularly for wireless systems operating at lower frequencies, such as the 5 GHz U-NII band, which is used for a broad range of wireless LAN, biomedical, space and other applications.